1) Field of the Invention
The field of invention is related to electronic design tools and automation, and more specifically to methods and systems for facilitating electronic circuit and chip design using resources accessible over a distributed electronic network such as the Internet.
2) Background
The electronics industry produces ever more advanced chip and circuit designs with the assistance of continuously improving design and verification tools. Chip designs and in particular System on Chip (SoC) designs may contain tens of millions of gates per chip, and will soon be in the range hundreds of millions of gates per chip. Engineers generally require advanced software tools to lay out a chip design and to help manage the huge volume of information associated therewith.
In a high-level view of the electronic design process, a design team takes a product idea from conception to completion over a period of time referred to as xe2x80x9ctime-to-market.xe2x80x9d Increased competition has resulted in immense pressure to reduce time-to-market with new products, because the first company to the market with a new product can typically expect to capture and hold a large market share against later competitors. In this environment, a difference as small as a few days between the planned and the actual shipment of a product may make an enormous difference in its profitability and in the revenue it generates.
In the present environment for designing large-scale circuits and complex chips, time and personnel are often short, and budgets are tight. A recent trend to increase design speed and efficiency involves the re-use or recycling of electronic circuit blocks or subsystems, which are alternatively referred to as xe2x80x9ccoresxe2x80x9d, xe2x80x9cvirtual component blocksxe2x80x9d or xe2x80x9cIPsxe2x80x9d (an acronym for xe2x80x9cIntellectual Properties,xe2x80x9d which denotes the proprietary nature of these pre-packaged circuit blocks). Once the design for a virtual component block has been tested and verified, it can be re-used in other applications that may be completely distinct from the application which led to its original creation. Other design groups within the same company as the original designers may achieve this re-use. Alternatively, this re-use may be achieved by other third parties, which purchase, license or transfer the IPs and incorporate the IPs into new designs. For example, an Application Specific Integrated Circuit (ASIC), as used in a cellular phone subsystem, may contain several cores such as a micro-controller as well as a digital signal processor and other components. Although the ASIC as a whole performs a specific function as a cellular phone subsystem, each of the cores within the ASIC design may have a generic use that may be used in other ASICs. After the design for the cellular phone subsystem has been tested and verified, each core could be re-used (as a virtual component block) in, for example, an automotive application. Design reuse of virtual component blocks allows a designer to complete a design much faster than building the entire design from scratch, and avoids the need for debugging, testing and verification of the subsystems embodied in the virtual component block. Examples of virtual circuit blocks or IP cores that are commercially available at present include Viterbi decoders, microcontrollers, digital/analog converters, and encryption/decryption processors, to name a few.
While virtual circuit blocks (i.e., IP cores) provide a means for reducing time-to-market by allowing for the purchase of standard blocks of code, there are a number of barriers to the convenient sale and use of virtual circuit blocks. Although, the re-use of prior core designs reduces total design time the initial search for prior core designs meeting the design criteria of the new ASIC design is in and of itself time consuming and tedious. With regard to quality assurance, for example, there are few, if any, standard methodologies for a designer to be assured of the quality of a virtual circuit block or its suitability for a particular design. Conversely, there are few, if any, standard methodologies for a seller of virtual circuit blocks to demonstrate the quality of the products to prospective customers. Another barrier is protection of the code and/or data comprising the virtual circuit block. Companies providing virtual circuit blocks are in need of a way to track the usage of their products and to protect the code and/or data in those blocks against theft, and such methodologies are preferably unobtrusive, yet allow full access to information required to incorporate those IP cores into a design. Another issue is data format. A virtual circuit block purchased for use in a circuit design must be compatible with the data formats used in that design. However, standards for interfacing with virtual circuit blocks, if they exist, are still evolving. As a result, becoming familiar with an interface format for a virtual circuit block may require a significant amount of work, as well as integrating a virtual circuit block into a circuit design, thus reducing the time advantage obtained through the use of the virtual circuit block. Transaction overhead in the form of high sales and legal costs also discourages sale and use of virtual circuit blocks. For example, legal review by one or both parties is often required with regard to the licensing of virtual circuit blocks.
Another drawback with the present way in which design and verification tools are acquired and used relates to technical support. Vendors often have help lines available to users needing technical support for a given software tool. However, assuming that the engineer gets past the frustrating maze of voicemail and one or more layers of less-knowledgeable first-line support personnel which typically characterize vendor help lines, it often takes a long time for the engineer to explain, and for the support personnel to resolve, an issue with a complex tool as applied to a complex circuit. For serious problems, the vendor may send a field applications engineer to the job site, but it is expensive to do so, and several days may pass before a field applications engineer arrives. During that time, the entire design project may remain at a standstill.
Component selection is also an area that suffers from inefficiencies and unnecessary time delays. An engineer may consult printed catalogs put out by component distributors to learn about and select parts, or may, using the Internet, visit a website of a supplier of manufacturer, where information about components may be found, or may use a search engine to try to gather product information on the Internet. However, searching the Internet for individual components can be time-consuming and tedious. Further, current search engines and methodologies are inefficient and incomplete, and may thus return search results that do not include websites offering components that a designer could beneficially use in a design. Engineers also may receive unsolicited data sheets from manufacturers, but such data sheets are often discarded, lost or forgotten about. Conversely, while the engineer might easily receive data such as IP I/O diagram or other top-level information, engineers may have difficulty receiving vital design information regarding the selected components. As part of the design process it is necessary for the engineers to obtain support data for each of the selected components. With increasing pressures to decrease time to market, it has become more difficult for engineers to spend time talking to supplier or distributor sales representatives, exacerbating the problem of information gathering about components.
Another problem experienced with the chip design process is that knowledge concerning design and verification processes are fragmented, and it is difficult to capture and maintain such knowledge. Attempting to discern through observation and study the individual design processes of many individual engineers is very challenging. Moreover, the design process can rarely be discerned from final blueprints or products, and is generally difficult to determine from draft or working documents. Different engineers will approach design in different fashions, which they may not even be able to articulate. Interviewing engineers to obtain data about the engineering design process is likely to be unproductive, and to consume a tremendous amount of time for a comparatively small payoff. Thus, benefits in training and improved methodologies that could result from metrics regarding the engineering design process continue to go unrealized.
Some attempts at addressing problems caused by fragmented design and verification processes involve exclusive partnering arrangements among companies that specialize in different areas of the design and verification process, in order to narrow the range of products and services that need to be learned by engineers and supported by internal technical staff. For example, a partnership of electronic design companies may include a provider of design verification tools, a provider of electronic components, and a company that ties them together. In the partnership model, compatibility issues can be addressed more easily, because a limited number of companies are involved. Further, increased revenue is created by influencing a customer of one partner at one phase of the design process to utilize the products or services of another partner in a different phase of the design process. However, a partnering arrangement drastically reduces the choices available to a design team, and may prevent the most optimum product from being used.
One approach for expediting the design process is to provide certain types of design and verification toolsxe2x80x94in particular, FPGA synthesis toolsxe2x80x94at a remote computer farm that can be accessed over the Internet. Under this approach, the FPGA synthesis tools are run on a central server farm, or computer farm, owned by a single applications service provider. A server farm, or computer farm, is generally a network of processors that are linked together to accomplish higher intensity computing tasks. In an illustrative system utilizing this approach, the applications service provider rewrites the interface of each offered FPGA synthesis tool in the Java(copyright) computing language, allowing usage of the tool on a wide variety of computing platforms and operating systems through standard, commercially available Internet browsers. A drawback of this approach is that the user is limited to the FPGA synthesis tools resident in the server farm of the applications service provider for which interface code has been written. Furthermore, the Java(copyright) language is notoriously slow, which can frustrate engineers and slow down the design and verification process.
It would be advantageous to connect participants in the electronic design process, including end users and suppliers, through a single portal site that facilitates information exchange and commercial transactions. It would further be advantageous to make a wide variety of design and verification tools readily and conveniently available to design engineers, and to allow use of such tools without a large initial capital outlay in either software or hardware. It would further be advantageous to provide a mechanism for pooling knowledge and information concerning chip design techniques, applications, products and tools. It would also be advantageous to provide a convenient means for allowing engineers to incorporate virtual circuit blocks into their designs.
The invention provides a platform which allows connection over a distributed electronic network, such as the Internet, to a plurality of end user systems to exchange and incorporate IP core designs into new complex circuit designs.
The embodiment provides a design platform in which designers may search multiple catalogs of IP designs and instantly transfer all relevant data regarding the IP into the files of a designer for use in designing new SoC. The platform of the embodiment supports the selection of either internal or external IP and TIP sourcing. The software supporting the design platform is written in modular form so that it may be easily adaptable to support the transfer of all relevant TIP data written in, for example, VHDL or Verilog. Moreover, the modular form of the platform support software allows the design platform the ability to support other hardware languages including developing languages such as System-C. The platform of the embodiment also allows the designer to set up all selected IPs within an overall design, connect the IPs and generate a Netlist of all of the components used in the overall design. The platform of the embodiment further provides an ANSI-C code output which may be compiled and easily used in any of a multitude of verification tools to ensure proper integration and connectivity, as well as basic functional verification of the overall design. Furthermore, the design platform may be customized or modified to generate a source code output in any of a plurality of assembly languages. Once IP selection, integration, and verification are performed, the platform of the embodiment is easily integrated with computer aided synthesis, placement and routing tools for final fabrication. Users accessing the design platform are presented with options in a menu or other convenient format identifying the tools and services available, and are able to more rapidly complete circuit designs by having access to a wide variety of tools and services in a single locale. The design platform may facilitate purchase, lease, or other acquisition of the tools and services offered through it.
In an embodiment, a design platform is implemented through an open portal site which acts as a server in the context of an n-tier client/server network, and allows electronic designers and design teams to utilize a wide variety of previously designed IPs. The open portal site invention in one aspect provides a platform which allows connection over a distributed electronic network, such as the Internet, to a plurality of end user systems to exchange and incorporate IP core designs into new complex circuit designs. In this embodiment, the portal site provides front-end hardware designers a means to search and get access to IPs of hardware components from both internal and external vendor sources. The portal site allows chip designers to search and access various IPs for incorporation into new chip designs. Furthermore, this embodiment allows the chip designer to transfer IP data and code directly through the portal site for immediate IP selection, sourcing, set-up, connection between various IPs, netlist generation. Additionally, an embodiment allows a chip designer to perform integration and connectivity verification as well as basic functional verification directly within the portal site. A platform to facilitate the portal site is written in JAVA to run on any computer and supports IPs written in various hardware implementation languages such as VHDL and Verilog. The software supporting the platform is written in modular form to allow for the support of new description implementation languages such as the developing System-C language.
In another embodiment, a closed portal site is provided on a network such as an Intranet to be used within a closed group of users. The embodiment may be provided as a closed portal site only accessible to a select number of users.
In another embodiment, the design platform is provided on a network of user workstations working together on a LAN. The design platform is written in JAVA to work directly on each user workstation.
Further embodiments, variations and enhancements are also described herein.